Various structures may be implemented in a computing system to checkpoint and recover a computer hardware architecture state throughout operation. Non-limiting examples of such structures may include a register file, a return stack, a dispatch queue, etc.
In one example, a computer hardware architecture state may be checkpointed upon entering a runahead mode of execution. In particular, during a runahead mode, speculative execution of instructions may cause an incorrect set of instructions to complete, and incorrectly update a computer hardware architecture state. Accordingly, a mechanism may be used to restore the hardware architecture state to an accurate pre-speculation state upon exiting the runahead mode.
In one example, a register file is used to checkpoint the computer hardware architecture state. The register file may be implemented as an array with a checkpointed bit for every functional bit. The register file may include control signals to indicate when to copy the functional bits to and recover from the checkpointed bits. For example, before entering the runahead mode, a ‘checkpoint’ control signal may be asserted to copy every functional bit (i.e., the contents of the register file) into a corresponding checkpointed bit. Similarly, upon exit from the runahead mode, a ‘recover’ signal may be asserted to copy every checkpointed bit back to the corresponding functional bit.
However, the above described register file implementation has some issues. For example, the register file is implemented by way of a customized static random access memory (RAM) having additional ports to accommodate the checkpoint and recover control signals as well as additional control logic necessary to implement the checkpoint and recover functionality. The customized RAM (a.k.a., the checkpointed RAM) may be more complex and costly to employ in a CPU relative to a RAM (a.k.a., a non-checkpointed RAM) that does not have additional ports and control logic integrated into it.
Furthermore, since all functional bits of the register file are copied to checkpointed bits upon entering the runahead mode and all checkpointed bits are restored to functional bits upon exiting the runahead mode, a substantial current draw and localized voltage drops may be incurred during each copy operation. Note that these issues may occur with any checkpointed structure that is implemented in this manner (i.e., an en-masse copy of bits). Accordingly, the power electronics of the CPU may have to be increased to accommodate such variations in power. The larger power electronics may consume more power relative to power electronics for a non-checkpointed RAM.